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Complies with Directive 2002/95/EC (RoHS) Product Overview
TRC102 is a highly integrated single chip, zero-IF, multi-channel, low power RF transceiver. It is an ideal fit for low cost, high volume, two way short-range wireless applications for use in the unlicensed 400-1000 MHz frequency bands. The TRC102 is FCC & ETSI certifiable and improves upon the TRC101 with improved phase noise and is capable of higher output power. All critical RF and baseband functions are completely integrated in the chip, thus minimizing external component count and simplifying and speeding design-ins. Use of a low cost, generic 10MHz crystal and a low-cost microcontroller is all that is needed to create a complete link. The TRC102 also incorporates different sleep modes to reduce overall current consumption and extend battery life. Its small size with low power consumption makes it ideal for various short range radio applications.
16-TSSOP package
Key Features
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Modulation: FSK (Frequency Hopping Spread Spectrum capability) Frequency range: 400-1000 MHz High sensitivity: (-112 dBm) High data rate: Up to 256 kbps Low current consumption (RX current ~11mA) Operating supply voltage: 2.2 to 3.8V Low standby current (0.3uA) Programmable Synch Byte Integrated PLL, IF, Baseband Circuitry Automatic Frequency Adjust(TX/RX frequency alignment) Programmable Analog/Digital Baseband Filter Programmable Output RF Power Programmable Input LNA Gain Internal Valid Data Recognition Transmit/Receive FIFO Standard SPI Interface TTL/CMOS Compatible I/O pins Programmable CLK Output Freq Automatic Antenna tuning circuit Low cost, generic 10MHz Xtal reference Integrated, Programmable Low Battery Voltage Detector Programmable Wake-up Timer with programmable Duty Cycle Integrated Selectable Analog/Digital RSSI Integrated Crystal Oscillator External Processor Interrupt pin Programmable Crystal Load Capacitance Programmable Data Rate Integrated Clock & Data Recovery Programmable FSK Deviation Polarity External Wake-up Events
*
Support for Multiple Channels * [433 Bands] 95 Channels (100kHz) * [868 Band] 190 Channels (100kHz) * [915 Band] 285 Channels (100kHz)
* * * *
Power-saving sleep mode Very few external components requirement Small size plastic package: 16-pin TSSOP Standard 13 inch reel, 2000 pieces.
Popular applications
* * * * * * * * * * * * Active RFID tags Automated Meter reading Home & Industrial Automation Security systems Two way Remote keyless entry Automobile Immobilizers Sports & Performance monitoring Wireless Toys Medical equipment Low power two way telemetry systems Wireless mesh sensors Wireless modules
RF Monolithics, Inc.
4441 Sigma Road Dallas, Texas 75244 (800) 704-6079 toll-free in U.S. and Canada www.rfm.com Email: info@rfm.com
Rev04
1
Table of Contents
Table of Contents........................................................................................................................2 1.0 TRC102 Pin Configuration ...................................................................................................2 1.1 Pin Description ..................................................................................................................3 2.0 Functional Description .........................................................................................................4 2.1 TRC102 Applications ........................................................................................................4 RF Transmitter Matching...................................................................................................4 Antenna Design Considerations........................................................................................5 PCB Layout Considerations ..............................................................................................5 3.0 TRC102 Functional Characteristics ....................................................................................7 Input/Output Amplifier .............................................................................................................7 Baseband Data and Filtering...................................................................................................7 Transmit Register....................................................................................................................8 Receive FIFO ..........................................................................................................................8 Programmable Synch Byte .....................................................................................................8 Automatic Frequency Adjustment (AFA).................................................................................9 Crystal Oscillator .....................................................................................................................9 Frequency Control (PLL) and Frequency Synthesizer ............................................................9 Data Quality Detector (DQD) ..................................................................................................9 Valid Data Detector ..............................................................................................................10 Receive Signal Strength Indicator (RSSI) .............................................................................10 OOK/ASK Signaling ..............................................................................................................10 Wake-Up Mode .....................................................................................................................10 Low Battery Detector.............................................................................................................11 SPI Interface .........................................................................................................................11 4.0 Control and Configuration Registers ................................................................................12 Status Register .....................................................................................................................13 Configuration Register [POR=8008h] ...................................................................................14 Automatic Frequency Adjust Register [POR=C4F7h] ...........................................................15 Transmit Configuration Register [POR=9800h] ....................................................................17 Transmit Register [POR=B8AAh]..........................................................................................18 Frequency Setting Register [POR=A680h] ...........................................................................19 Receiver Control Register [POR=9080h] ..............................................................................20 Baseband Filter Register [POR=C22Ch] ..............................................................................22 FIFO Read Register [POR=B000h].......................................................................................23 FIFO and RESET Mode Configuration Register [POR=CA88h] ...........................................24 Synch Byte Configuration Register [POR=CED4h]...............................................................26 Data Rate Setup Register [POR=C623h]..............................................................................27 Power Management Register [POR=8208h].........................................................................28 Wake-up Timer Period Register [POR=E196h] ....................................................................29 Duty Cycle Set Register [POR=C80Eh] ................................................................................30 Battery Detect Threshold and Clock Output Register [POR=C000h]....................................31 PLL Configuration Register [POR=CC67h]...........................................................................32 5.0 Maximum Ratings ...............................................................................................................33 6.0 DC Electrical Characteristics.............................................................................................33 7.0 AC Electrical Characteristics.............................................................................................34 Receiver Electrical Characteristics........................................................................................34 Transmitter Electrical Characteristics....................................................................................35 8.0 Receiver Measurement Results.........................................................................................37 9.0 Transmitter Measurement Results ....................................................................................39 10.0 Package Information.........................................................................................................40
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1. Pin Configuration
SDI SCK nCS SDO IRQ DATA/nFSEL CR/FINT/FCAP CLKOUT
1 2 3 4 5 6 7 8
TOP VIEW
16 15 14 13 12 11 10 9
TRC102
1.1 Pin Descriptions
Pin
1 2 3 4 5
nINT/DDET RSSIA VDD RF_N RF_P GND RESET Xtal/Ref
Name
SDI SCK nCS SDO nIRQ
Description
SPI Data In SPI Data Clock Chip Select Input - Selects the chip for an SPI data transaction. The pin must be pulled `low' for a 16bit read or write function. See Figure 6 for timing specifications. SPI Data Out Interrupt Request Output - The receiver will generate an active low interrupt request for the microcontroller on the following events: * The TX register is ready to receive the next byte * The FIFO has received the preprogrammed amount of bits * Power-on reset * FIFO overflow/TX register underrun * Wake-up timer timeout * Negative pulse on the interrupt input pin nINT * Supply voltage below the preprogrammed value is detected Data In - When the internal TX register is not used, this pin may be used to manually modulate data from an external host processor. If the internal TX register is enabled, this pin may be left unconnected or tied "High". When using the internal Rx FIFO, this pin must be pulled "Low". This pin is used to select the internal registers when reading and writing. Data Out - When the internal FIFO is not used this pin is used in conjunction with pin 7 (Recovered Clock) to receive data. FIFO Select - When reading the RX FIFO, this pin selects the FIFO and the first bit appears on the next clock. Use this pin in conjunction with Pin 7. This pin is internally pulled "High" when accessing the TX register. Leave this pin "High" when the TX register is enabled. For minimum current consumption do NOT pull this pin "Low" in Sleep Mode. Recovered Clock Output - When the digital filter is used (Baseband Filter Register, Bit [4]) and FIFO disabled (Configuration Register, Bit [6]), this pin provides the recovered clock from the incoming data. FIFO INT - When the internal FIFO is enabled (Configuration Register, Bit [6]), this pin acts as a FIFO Full interrupt indicating that the FIFO has filled to its pre-programmed limit (FIFO Configuration Register, Bit [7..4]). External Data Filter Capacitor - When the Analog filter is used (Baseband Filter Register, Bit [4]), this pin is the raw baseband data that may be used by a host processor for data recovery. The external capacitor forms a simple lowpass filter with an internal 10KOhm series resistor. The capacitor value may be chosen for a Max data rate up to 256kbps. Optional host processor Clock Output Xtal - Connects to a 10MHz series crystal or an external oscillator reference. The circuit contains an integrated load capacitor (See Configuration Register) in order to minimize the external component count. The crystal is used as the reference for the PLL, which generates the local oscillator frequency. The accuracy requirements for production tolerance, temperature drift and aging can be determined from the maximum allowable local oscillator frequency error. Whenever a low frequency error is essential for the application, it is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. Ext Ref - An external reference, such as an oscillator, may be connected as a reference source. Connect through a .01uF capacitor. Reset Output with internal pull-up System Ground RF Diff I/O RF Diff I/O Supply Voltage Analog RSSI Output - The Analog RSSI can be used to determine the actual signal strength. The response and settling time depends on an external filter capacitor. Typically, a 1000pF capacitor will provide optimum response time for most applications. nINT - This pin may be configured as an active low external interrupt to the chip. When a logic `0' is applied to this pin, it causes the nIRQ pin (5) to toggle, signaling an interrupt to an external processor. Reading the first four (4) bits of the status register tells the source of the interrupt. This pin may be used as a wake-up event from sleep. Valid Data Detector Output- This pin may be configured to indicate Valid Data when the synchronous pattern recognition circuit indicates potentially real incoming data.
6
Data/nFSel
7
CR/FINT/FCAP
8 9
ClkOut Xtal/Ref
10 11 12 13 14 15
nRESET GND RF_P RF_N VDD RSSIA
16
nINT/DDet
3
2. Functional Description
The TRC102 is a low power, frequency agile, zero-IF, multi-channel FSK transceiver for use in the 433, 868, and 916 MHz bands. All RF and baseband functions are completely integrated requiring only a single 10MHz crystal as a reference source and an external low-cost processor. Functions include: * PLL synthesizer * Power Amp * LNA * I/Q Mixers * I/Q Demodulators * Baseband Filters * Baseband Amplifiers * RSSI * Low Battery Detector * Wake-up Timer/Duty Cycle Mode * Valid Data Detection/Data Quality The TRC102 is ideal for Frequency Hopping Spread Spectrum (FHSS) applications requiring frequency agility to meet FCC and ETSI requirements. Use of a low-cost microcontroller is all that is needed to create a complete data link. The TRC102 incorporates different sleep modes to reduce overall current consumption and extend battery life. It is ideal for applications operating from typical lithium coin cells.
2.1 TRC102 Typical Application Circuit
Figure 1. Typical Application Circuit for Monopole Antenna (50 Ohm Load)
RF Transmitter Matching The RF pins are high impedance and differential. The optimum differential load for the RF port at a given frequency band is shown in Table 1. TABLE 1. TRC102 Admittance Impedance (Ohm) L 433 MHz 1.4e-3 - j7.1e-3 27 + j136 52nH 868 MHz 2e-3 - j1.5e-2 8.7 + j66 12.5nH 916 MHz 2.2e-3 - j1.55e-2 9 + j63 11.2nH
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These values are what the RF port pins want to "see" as an antenna load for maximum power transfer. Antennas ideally suited for this would be a Dipole, Folded Dipole, and Loop. For all transmit antenna applications a bias or "choke" inductor must be included since the RF outputs are open-collector type. The TRC102 may also drive a single ended 50 Ohm load, such as a monopole antenna, using the matching circuit as shown in Figure 1. Use of a balun would provide an optimum power transfer, but the matching circuit of Figure 1 has been optimized for use with discrete components, reducing the cost associated with use of a balun. The matching component values for a 50 Ohm load for each band are given in Table 2. Table 2. Ref Des 433 868 916 C1 5.1pF 2.7pF 2.7pF C2 2.7pF 1.2pF 1.2pF C4 .1uF .1uF .1uF C7 100pF 100pF 100pF L1 36nH 8.7nH 8.7nH L2 390nH 100nH 100nH L3 47nH 22nH 22nH
Antenna Design Considerations The TRC102 was designed to drive a differential output such as a Dipole antenna or a Loop. The loop antenna is ideally suited for applications where compact size is required. The dipole is typically not an attractive option for compact designs due to its inherent size at resonance and distance needed away from a ground plane to be an efficient antenna. A monopole antenna can be used with the addition of a balun or by using the matching circuit in Figure 1. PCB Layout Considerations Optimal PCB layout is very critical. For optimal transmit and receive performance, the trace lengths at the RF pins must be kept as short as possible. Using small, surface mount components, like 0402 or 0603, will yield the best performance as well as keep the RF port compact. Make all RF connections short and direct. A good rule of thumb to adhere to is add 1nH of series inductance for every 0.1" of trace length. The crystal oscillator is also affected by additional trace length as it adds parasitic capacitance to the overall load of the crystal. To minimize this effect place the crystal as close as possible to the chip and make all connections short and direct. This will minimize the effects of "frequency pulling" that stray capacitance may introduce and allows the internal load capacitance of the chip to be more effective in properly loading the crystal oscillator circuit. If using an external processor, the TRC102 provides an on-chip clock for that purpose. Even though this is an integrated function, long runs of the clock signal may radiate and cause interference. This can degrade receiver performance as well as add harmonics or unwanted modulation to the transmitter. Keep clock connections as short as possible and surround the clock trace with an adjacent ground plane pour where needed. This will help in reducing any radiation or crosstalk due to long runs of the clock signal. Good power supply bypassing is also essential. Large decoupling capacitors should be placed at the point where power is applied to the PCB. Smaller value decoupling capacitors should then be placed at each power point of the chip as well as bias nodes for the RF port. Poor bypassing lends itself to conducted interference which can cause noise and spurious signals to couple into the RF sections, significantly reducing performance.
5
Assembly View
Top Side
Bottom Side
6
3. TRC102 Functional Characteristics
FSK I/Q DE MOD ASK
+ -
LNA
0/90
S DI S DO S CK nCS CONT ROL LOGIC nIRQ DA T A / nF S E L CR/F INT /F CA P
RF _P RF _N
RS S I T X /RX
PA
V CO
P LL
OS C
CLK OUT nINT /DDE T
/N
B A T T DE T
R
X T A L/RE F
RS S IA
V DD
GND
nRE S E T
Figure 2. Functional Block Diagram
Input/Output Amplifier The output power amplifier is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna. Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during production and to offset "hand effects". Registers common to the Power Amplifier are: * Power Management Register * Transmit Configuration Register The input LNA has selectable gain (0dB, -6dB, -14dB, -20dB) which may be useful in an environment with strong interferers. The LNA has a 250Ohm differential input impedance which requires a matching circuit when connected to 50 Ohm devices. Registers common to the LNA are: * Power Management Register * Receiver Control Register Baseband Data and Filtering The baseband receiver has several programmable options that optimize the data link for a wide range of applications. The programmable functions include: * Receive bandwidth * Receive data rate * Baseband Analog Filter * Baseband Digital Filter * Clock Recovery (CR) * Receive FIFO * Data Quality Detector * Valid Data Detector The receive bandwidth is programmable from 67kHz to 400kHz to accommodate various FSK modulation deviations. If the deviation is known for a given transmitter, the best results are obtained with a bandwidth at least twice the transmitter FSK deviation.
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The receive data rate is programmable from 337bps to 256kbps. An internal prescaler is used to give better resolution when setting up the receive data rate. The prescaler is optional and may be disabled through the Data Rate Setup Register. The type of baseband filtering is selectable between an Analog filter and a Digital filter. The analog filter is a simple RC lowpass filter. An external capacitor may be chosen depending on the actual data rate. The chip has an integrated 10K Ohm resistor in series that makes the RC lowpass network. With the analog filter selected, a maximum data rate of 256kbps can be achieved. The digital filter is used with a clock frequency of 29X data rate. In this mode a clock recovery (CR) circuit is used to provide for a synchronized clock source to recover the data using an external processor. The CR has three modes of operation: fast, slow, and automatic, all configurable through the Baseband Filter Register. The CR circuit works by sampling the preamble on the incoming data. The preamble must contain a series of 1's and 0's in order for the CR circuit to properly extract the data timing. In slow mode the CR circuit requires more sampling (12 to 16 bits) and thus has a longer settling time before locking. In fast mode the CR circuit takes fewer samples (6 to 8 bits) before locking so settling time is not as long and timing accuracy is not critical. In automatic mode the CR circuit begins in fast mode to coarsely acquire the timing period with fewer samples and then changes to slow mode after locking. Further details of the CR and data rate clock are provided in the Baseband Filter Register. CR is only used with the digital filter and data rate clock. These are not used when configured for the analog filter. Transmit Register The transmit register is configured as two 8-bit shift registers connected in series to form a single 16-bit shift register. On POR the registers are filled with the value AAh. This can be used to generate a preamble before sending actual data, however, the value is not reloaded when the transmit register is reenabled. When the transmitter is enabled through the Power Management Register, transmission begins immediately and the value in the transmit register begins to be sent out. If there is nothing written to the register then it will send out the default value AAh. The next data byte can be loaded via the SPI bus to the transmit register by monitoring the SDO pin for a logic `1' or waiting for an interrupt from the nIRQ pin. After data has been loaded to the transmit register the processor must wait for the next interrupt before disabling the transmitter or the rest of the data left in the register will be lost. Inserting a dummy byte of all 0's is recommended for the last byte of data loaded. Receive FIFO The receive FIFO is configured as one 16-bit register. The FIFO can be configured to generate an interrupt after a predefined number of bits have been received. This threshold is programmable from 1 to 15 bits. It is recommended to set the threshold to at least half the length of the register (8 bits) to insure the external host processor has time to set up. The receive FIFO may also be configured to fill only when valid data has been identified. The TRC102 has a synchronous pattern detector that watches incoming data for a particular pattern. When it sees this pattern it begins to store any data that follows. At the same time, if pin 16 is configured for Valid Data Detector output (See Receiver Control Register), this pin will go `high' signaling valid data. This can be used to prepare a host processor for retrieving data. The internal synchronous pattern is user programmable. The FIFO can be read out through the SDO pin only by toggling the nFSEL pin (6) which selects the FIFO for read and reading out data on the next clock. The FINT pin (7) will stay active (logic `1') until the last bit has been read out, and it will then go `low'. This pin may also be polled to watch for valid data. When the number of bits received in the FIFO match the pre-programmed limit, this pin will go active (logic `1') and stay active until the last bit is read out as above. An alternative method of reading the FIFO is through an SPI bus Status Register read. The drawback to this is that all interrupt and status bits must be read first before the FIFO bits appear on the bus. This could pose a problem for receiving large amounts of data. The best method is using the SDO pin and the associated FIFO function pins. Programmable Synch Byte The TRC102 may be configured to use a synch character to signal valid incoming data. This character is divided into two bytes, SB1 and SB0. SB1 is fixed to 2Dh and is not programmable. SB0 is user configurable. The synch character may also be configured as a byte character or a word character. A 8
byte character uses only SB0, which is user configurable. A word character uses both SB1 and SB0 with the lower byte SB0 being user configurable. This becomes an advantage when operating near other interferers or identifying specific transmitters. Automatic Frequency Adjustment (AFA) The PLL has the capability to do fine adjustment of the carrier frequency automatically. In this way, the receiver can minimize the offset between transmit and receive frequency. This function may be enabled or disabled through the Automatic Frequency Adjustment Register. The range of offset can be programmed as well as the offset value calculated and added to the frequency control word within the PLL to incrementally change the carrier frequency. The chip can be programmed to automatically perform an adjustment or may be manually activated by a strobe signal. This function has the advantage of allowing: * Low cost, lower accuracy crystals to be used * Increased receiver sensitivity by narrowing the receive bandwidth * Achieving higher data rates Crystal Oscillator The TRC102 incorporates an internal crystal oscillator circuit that provides a 10MHz reference, as well as internal load capacitors. This significantly reduces the component count required. The internal load capacitance is programmable from 8.5pF to 16pF in 0.5pF steps. This has the advantage of accepting a wide range of crystals from many different manufacturers having different load capacitance requirements. Being able to vary the load capacitance also helps with fine tuning the final carrier frequency since the crystal is the PLL reference for the carrier. The crystal oscillator circuit is sensitive to parasitic capacitance for startup. Only a slight amount of parasitic capacitance is needed to facilitate oscillation. A recommended solution is to apply a ground plane around the crystal and widen the connection to the TRC102. If this is not possible, a 0.5-1pF capacitor soldered across the crystal will initiate startup. An external clock signal is also provided that may be used to run an external processor. This also has the advantage of reducing component count by eliminating an additional crystal for the host processor. The clock frequency is also programmable from eight pre-defined frequencies, each a pre-scaled value of the 10MHz crystal reference. These values are programmable through the Battery Detect Threshold and Clock Output Register. The internal clock oscillator may be disabled which also disables the output clock signal to the host processor. When the oscillator is disabled, the chip provides an additional 196 clock cycles before releasing the output, which may be used by the host processor to setup any functions before going to sleep. Frequency Control (PLL) and Frequency Synthesizer The PLL synthesizer is the heart of the operating frequency. It is programmable and completely integrated, providing all functions required to generate the carriers and tunability for each band. The PLL requires only a single 10MHz crystal reference source. RF stability is controlled by choosing a crystal with the particular specifications to satisfy the application. This gives the designer the maximum flexibility in performance. The PLL is able to perform manual and automatic calibration to compensate for changes in temperature or operating voltage. When changing band frequencies, re-calibration must be performed. This can be done by disabling the synthesizer and re-enabling again through the Power Management Register. Registers common to the PLL are: * Power Management Register * Configuration Register * Frequency Setting Register * Automatic Frequency Adjust Register * Transmit Configuration Register Data Quality Detector (DQD) The DQD is a unique function of the TRC102. The DQD circuit looks at the prefiltered incoming data and counts the "spikes" of noise for a predetermined period of time to get an idea of the quality of the link. This parameter is programmable through the Data Filter Command Register. The DQD count threshold is 9
programmable from 0 to 7 counts. The higher the count the lower the quality of the data link. This means the higher the content of noise spikes in the data stream the more difficult it will be to recover clock information as well as data. Valid Data Detector The DDET is an extension of the DQD. When incoming data is detected, it uses the DQD signal, the Clock Recovery Lock signal, and the Digital RSSI signal to determine if the incoming data is valid. The DDET looks for valid data transitions at an expected data rate. The desired data rate and the acceptance criteria for valid data are user programmable through the SPI port. The DDET signal is valid when using either the internal receive FIFO or an external pin to capture baseband data. The DDET has three modes of operation: slow, medium, fast. Each mode is dependent on what signals it uses to determine valid data as well as the number of incoming preamble bits present at the beginning of the packet. The DDET can be disabled by the user so that only raw data from the comparator comes out, or it can be set to accept only a preset range of data rates and data quality. The DDET saves battery power and time for a host microprocessor because it will not wake up the microprocessor unless there is valid data present. See the Receiver Control Register for a detailed description of the setup for valid data. Receive Signal Strength Indicator (RSSI) The TRC102 provides an analog RSSI and a digital RSSI. The digital RSSI threshold is programmable through the Receiver Control Register and is readable through the Status Register only. When an incoming signal is stronger than the preprogrammed threshold, the digital RSSI bit in the Status Register is set. The analog RSSI is available through the RSSIA external pin (15). This pin requires an external capacitor which sets the settling time. The analog RSSI may be used to recover ASK modulated data at a low rate on the order of a few thousand bits per sec. The external capacitor value will control the received ASK data rate allowed so choosing a lower value capacitor enables recovery of faster data at the expense of amplitude. Using pin (15) with a sensitive comparator will yield good results. OOK/ASK Signaling The RSSI may be used to recover an OOK/ASK signal using an external comparator, capacitively coupled to the RSSI output. Typically, Automatic Gain Control (AGC) is used to reduce the input signal level upon saturation of the RSSI in the presence of strong or near-field ASK signals. The TRC102 does not have an AGC option, however, the input LNA gain is programmable. The output RSSI signal level may be sampled upon enabling of the receiver to test if the signal level is in saturation. If saturation is confirmed, the input LNA gain may be reduced until the RSSI output signal level falls within the RSSI deviation range. Wake-Up Mode The TRC102 has an internal wake-up timer that has very low current consumption (1.5uA typical) and may be programmed from 1ms to several days. A calibration is performed to the crystal at startup and every 30 sec thereafter, even if in sleep mode. If the oscillator circuit is disabled the calibration circuit will turn it on briefly to perform a calibration to maintain accurate timing and return to sleep. The TRC102 also incorporates other power saving modes aside from the wake-up timer. Return to active mode may be initiated from several external events: * Logic `0' applied to nINT/DDET pin (16) * Low Supply Voltage Detect * FIFO Fill * SPI request If any of these wake-up events occur, including the wake-up timer, the TRC102 generates an external interrupt on the nIRQ pin (5) which may be used as a wake-up signal to a host processor. The source of the interrupt may be read out from the Status Register over the SPI bus.
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Low Battery Detector The integrated low battery detector monitors the voltage supply against a preprogrammed value and generates an interrupt when the supply voltage falls below the programmed value. The detector circuit has 50mV of hysteresis built in. SPI Interface The TRC102 is equipped with a standard SPI bus that is compatible to almost all SPI devices. All functions and status of the chip are accessible through the SPI bus. Typical SPI devices are configured for byte write operations. The TRC102 uses word writes so the nCS pin(3) should be pulled low for 16 bits.
Figure 3. SPI Interface Timing
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4. Control and Configuration Registers
Bit 15
STATUS CONFIG AFA TX CONFIG TX REG FREQ SET RECV CTRL BASEBAND FIFO READ FIFO/RESET CONFIG SYNCH CHAR DATA RATE SET POWER MANAGEMENT WAKE-UP PERIOD DUTY CYCLE SET BATT DETECT PLL CONFIG
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 14
0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 1
Bit 13
0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0
Bit 12
0 0 1 1 0 1 0 1 0 0 0 0 R4 0 0 0
Bit 11
0 0 1 1 Freq11 0 0 0 1 1 0 0 R3 1 0 1
Bit 10
LB 0 1 0 0 Freq10
Bit 9
0 0 0 0 Freq9
Bit 8
0 0 MODP 0 Freq8 VDIR0 0 0 0 0 0 0 R0 0 0 0
Bit 7
Bit 6
Bit 5
BAND1 RNG1 DEV1 TX5 Freq5 BB0 1 RX5 FINT1
Bit 4
BAND0 RNG0 DEV0 TX4 Freq4 GAIN1 FILT RX4 FINT0 SYNC4 BITR4
Bit 3
OFF3 CAP3 STRB 0 TX3 Freq3 GAIN0 1 RX3 0
Bit 2
OFF2 CAP2 ACCF PWR2 TX2 Freq2 RSSI2
Bit 1
OFF1 CAP1 OFFEN PWR1 TX1 Freq1 RSSI1
Bit 0
OFF0 CAP0 AFEN PWR0 TX0 Freq0 RSSI0
POR Value
-8008h C4F7h 9800h B8AAh A680h 9080h
FIFTXRX POR FIFOV/UR WKINT INTRST
FIFEMP RSSI/AT GDQD
CRLK AFATGL OFFSGN
DATEN FIFEN AUTO1 AUTO0 DEV3 TX7 Freq7 BB2 CRLK RX7 FINT3 DEV2 TX6 Freq6 BB1 CRLC RX6 FINT2
INT/VDI VDIR1 0 0 0 1 1 0 R2 0 0 1 1 0 1 1 1 1 R1 0 0 0
DQLVL2 DQLVL1 DQLVL0 C22Ch RX2 FIFST RX1 FILLEN SYNC1 BITR1 RX0 B000h
RSTEN CA80h SYNC0 CED4h BITR0 C623h 8208h E196h C80Eh C000h
SYNC7 SYNC6 SYNC5 PRE RXEN MUL7 DC6 CLK2 0 BITR6 BBEN MUL6 DC5 CLK1 BUF1 BITR5 TXEN MUL5 DC4 CLK0 BUF0
SYNC3 SYNC2 BITR3 BITR2
SYNEN OSCEN LBDEN WKUPEN CLKEN MUL4 DC3 LBD4 XSU MUL3 DC2 LBD3 PDD MUL2 DC1 LBD2 DITH MUL1 DC0 LBD1 1 MUL0 DCEN LBD0
PLLBW CC67h
12
Status Register (Read Only)
Bit 15
FIFTXRX
Bit 14
POR
Bit 13
FIFOV/UR
Bit 12
WKINT
Bit 11
INTRST
Bit 10
LB
Bit 9
FIFEMP
Bit 8
RSSI/AT
Bit 7
GDQD
Bit 6
CRLCK
Bit 5
AFATGL
Bit 4
OFFSGN
Bit 3
OFF3
Bit 2
OFF2
Bit 1
OFF1
Bit 0
OFF0
The Status Register provides feedback for: * FIFO ready/full/empty/under run/overwrite * POR * Interrupt state * Low Battery * Good Data Quality * Digital RSSI signal level * Clock Recovery * Frequency Offset value and sign * AFA Note: The Status Register read command begins with a logic `0' where all other register commands begin with a logic `1'. Bit [15]:FIFTXRX - When set, indicates the transmit register is ready to receive the next byte for transmission (Transmit Mode) or that the Rx FIFO has reached the preprogrammed limit (Receive Mode). This bit is multiplexed and dependent on whether you are in the respective Transmit or Receive mode. (Cleared when FIFO read). Bit [14]:POR - When set, Power-on Reset occurred. (Cleared after Status Reg read). Bit [13]:FIFOV/UR - When set, indicates transmit register under run or register overwrite (Transmit Mode) or receive FIFO overflow (Receive Mode). (Cleared after Status Reg read). Bit [12]:WKINT - When set, indicates a Wake-up timer overflow. (Cleared after Status Reg read). Bit [11]:INTRST - When set, indicates a High to Low logic level change on interrupt pin (pin 16). (Cleared after Status Reg read). Bit [10]:LB - When set, indicates the supply voltage is below the preprogrammed limit. See Battery Detect Threshold and Clock Output Register. Bit [9]:FIFEMP - When set, indicates receive FIFO is empty. Bit [8]:RSSI(Rx) - When set and chip in receive mode, this bit indicates that the incoming RF signal is above the preprogrammed Digital RSSI limit. AT(TX) - When in transmit mode this bit indicates that the antenna tuning circuit has detected a strong enough RF signal. Bit [7]:GDQD - When set, indicates good data quality. Bit [6]:CRLCK - When set, indicates Clock Recovery is locked. Bit [5]:AFATGL - For each AFC cycle run, this bit will toggle between logic `1' and logic `0'. Bit [4]:OFFSGN - Indicates the difference in frequency is higher (logic `1') or lower (logic `0') than the chip frequency. Bit [3..0]:OFF[3..0] - The offset value to be added to the frequency control word (internal PLL). To read the status register, initiate a command beginning with a `0' and read the remaining bits on the SDO line. All other commands begin with a `1' so the TRC102 recognizes a command vs. status. See figure 4 for timing reference.
nCS
Figure 4. Status Read Timing
13
Configuration Register [POR=8008h]
Bit 15
1
Bit 14
0
Bit 13
0
Bit 12
0
Bit 11
0
Bit 10
0
Bit 9
0
Bit 8
0
Bit 7
DATEN
Bit 6
FIFEN
Bit 5
BAND1
Bit 4
BAND0
Bit 3
CAP3
Bit 2
CAP2
Bit 1
CAP1
Bit 0
CAP0
The configuration register sets up the following: * Internal Data Register * Internal FIFO * Frequency Band in use * Crystal Load capacitance Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the configuration register. Bit [7] - Data Register Enable: This bit enables the internal data register when set. If the internal data register is used, the FSK pin (6) must be connected to GND. Bit [6] - FIFO Enable: This bit enables the internal data FIFO when set. The FIFO is used to store data during receive. If the FIFO is disabled by clearing this bit, pin 6 (Data) and pin 7 (Recovered Clock) are used to receive data. See Data Buffer Setup Register section for details on the FIFO configuration. Bit [5..4] - Band Select: These bits set the frequency band to be used. There are four (4) bands that are supported. See Table 3 below for Band configuration. TABLE 3. Frequency Band BAND1 433 0 868 1 916 1
BAND0 1 0 1
Bit [3..0] - Load Capacitance Select: These bits set the load capacitance for the crystal reference. The internal load capacitance can be varied from 8.5pF to 16pF in 0.5pF steps to accommodate a wide range of crystal vendors as well as adjust the reference frequency and compensate for stray capacitance that may be introduced due to PCB layout. See Table 4 below for load capacitance configuration. TABLE 4. CAP3 0 0 0 0 1 1 CAP2 0 0 0 0 ...... 1 1 CAP1 0 0 1 1 1 1 CAP0 0 1 0 1 0 1 Crystal Load Capacitance 8.5 9 9.5 10 ...... 15.5 16
14
Automatic Frequency Adjust Register [POR=C4F7h]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 1 Bit 9 0 Bit 8 0 Bit 7 AUTO1 Bit 6 AUTO0 Bit 5 RNG1 Bit 4 RNG0 Bit 3 STRB Bit 2 ACCF Bit 1 OFFEN Bit 0 AFEN
The AFA (Automatic Frequency Adjust) Register configures: * Manual or Automatic frequency offset adjustment * Calculation of the offset value and write to the Status Register * Fine offset adjustment control The AFA (Automatic Frequency Adjust) Register controls and configures the frequency adjustment range and mode for keeping the transmitter and receiver frequency locked, providing for an optimal link. The AFA may be manually controlled by an external processor by asserting a strobe signal to initiate a sample, or may be setup for automatic operation, which uses the Valid Data Detector (VDI) signal to initiate a frequency adjustment. When the VDI goes active, the AFA circuit performs a sample and updates the offset register automatically. The elapsed time for an AFA is determined by the setting of the clock recovery (CR) bit in the Baseband Filter Register. The AFA also calculates the offset of the transmit and receive frequency. This offset value is included in the status register read and the AFA must be disabled during the status read to ensure reporting good offset accuracy. Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Automatic Frequency Adjust Register. Bit [7..6] - Mode Selection: These bits select Automatic or Manual operation. When set to Manual operation, the TRC102 will take a sample when a strobe signal (See Bit [3]) is written to the register. There are four modes of operation. See Table 5 below for configuration. TABLE 5. Automatic fOFFSET Mode Mode Off Run Once after Pwr-up Keep offset during Rcv ONLY Keep offset indep of VDI state AUTO1 0 0 1 1 AUTO0 0 1 0 1
Mode(0,1) - The circuit takes a measurement only once after power-up. Mode(1,0) - When the Valid Data Detector (VDI) pin is low, indicating poor receiving conditions, the offset register is automatically cleared. Use this setting when receiving from several different transmitters that are operating very close to the same frequencies so that the receiver may align itself on each transmission from a different transmitter. Mode(1,1) - This setting is best used when receiving from a single transmitter. The measured offset value is kept independent of the state of the VDI signal. Once the link is aligned it may be manually toggled by the user.
15
Automatic Frequency Adjust Register (continued)
Bit [5..4] - Allowable Frequency Offset: These bits select the amount of offset allowable between Transmitter and Receiver frequencies. The allowable range can be specified as in Table 6 below. TABLE 6. Freq Offset Range RNG1 No Limit 0 +15*fres/-16*fres 0 +7*fres /-8*fres 1 +3*fres /-4*fres 1 RNG0 0 1 0 1
where fres is the tuning resolution for each band as follows: fres: 433 MHz Band = 2.5kHz 868 MHz Band = 5kHz 916 MHz Band = 7.5kHz
Bit [3] - Manual Frequency Adjustment Strobe: This bit is the strobe signal that initiates a manual frequency adjustment sample. When set, a sample of the received signal is compared to the Receiver LO signal and an offset is calculated. If enabled, this value is written to the Offset Register (See Bit [1]) and added to the frequency control word of the PLL. This bit MUST be reset before initiating another sample. Bit [2] - High Accuracy (Fine) Mode: This bit, when set, switches the frequency adjustment mode to high accuracy. In this mode the processing time is twice the regular mode, but the uncertainty of the measurement is significantly reduced. Bit [1] - Frequency Offset Register Enable: This bit, when set, enables the offset value calculated by the offset sample to be added to the frequency control word of the PLL that tunes the desired carrier frequency. Bit [0] - Offset Frequency Enable: This bit, when set, enables the TRC102 to calculate the offset frequency by the sample taken from the Automatic Frequency Adjustment circuit.
16
Transmit Configuration Register [POR=9800h]
Bit 15 1 Bit 14 0 Bit 13 0 Bit 12 1 Bit 11 1 Bit 10 0 Bit 9 0 Bit 8 MODP Bit 7 DEV3 Bit 6 DEV2 Bit 5 DEV1 Bit 4 DEV0 Bit 3 0 Bit 2 PWR2 Bit 1 PWR1 Bit 0 PWR0
The Transmit Configuration Register configures: * Modulation Polarity * Modulation Bandwidth * Output Transmit Power Bit [15..9] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Transmit Configuration Register. Bit [8] - Modulation Polarity: When clear, a logic `0' is defined as the lower channel frequency and a logic `1' as the higher channel frequency (positive deviation). When set, a logic `0' is defined as the higher channel frequency and a logic `1' as the lower channel frequency (negative deviation). Bit [7..4] - Modulation Bandwidth: These bits set the FSK frequency deviation for transmitting a logic `1' and logic `0'. The deviation is programmable from 15kHz to 240kHz in 15kHz steps. See Table 7 below for deviation settings. TABLE 7.
Modulation Bandwidth 15 kHz 30 kHz 45 kHz 60 kHz 75 kHz 90 kHz 105 kHz 120 kHz 135 kHz 150 kHz 165 kHz 180 kHz 195 kHz 210 kHz 225 kHz 240 kHz Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F DEV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DEV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DEV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DEV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bit [3] - Not used. Write as logic `0'. Bit [2..0] - Output Transmit Power: These bits set the transmit output power. The output power is programmable from Max to -21dB in -3dB steps. See Table 8 below for Output Power settings. TABLE 8.
Output Power (Relative) Max -3dB -6dB -9dB -12dB -15dB -18dB -21dB PWR2 0 0 0 0 1 1 1 1 PWR1 0 0 1 1 0 0 1 1 PWR0 0 1 0 1 0 1 0 1
17
Transmit Register [POR=B8AAh]
Bit 15 1 Bit 14 0 Bit 13 1 Bit 12 1 Bit 11 1 Bit 10 0 Bit 9 0 Bit 8 0 Bit 7 TX7 Bit 6 TX6 Bit 5 TX5 Bit 4 TX4 Bit 3 TX3 Bit 2 TX2 Bit 1 TX1 Bit 0 TX0
The Transmit Register holds the 8 bits to be transmitted. Bit [7] of the Configuration Register must be set (logic `1') in order to use this. If Bit [7] is not set, use pin 6 to manually modulate the data. The initial value on power-up of the register is AAh. This can be used to send a preamble signal by setting Bit [5] of the Power Management Register (See Figure 5 below). When this bit is set, transmission begins immediately and the initial value AAh is sent. The SDO pin(4) may be monitored to see when the next byte of data may be written to the register (SDO is logic `1'). It is recommended that the register be preloaded with a preamble regardless of the POR value.
Initial Setup TXEN = 0
FIGURE 5. Power-up TX Register Setting Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Transmit Register. Bit [7..0] - Transmit Byte: The data byte to be sent is written here. As soon as the power amplifier is enabled the data byte is sent. The SDO pin(4) may be monitored to determine when the byte has been sent.
Sequential Byte Write Method (Recommended)
The transmit register may be continuously accessed by holding the nCS pin (3) `Low" for the duration of the data stream. On the first falling edge of nCS the register command should be issued as normal. Sequential byte writes to the register afterwards will load the transmit register directly without having to reissue the command byte. The SDO pin (4) may be used as a "Transmit Register Empty" flag to write the next byte.
nCS SCK SDI SDO
Figure 6. Sequential Byte Write Timing
COMMAND
DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
18
Frequency Setting Register [POR=A680h]
Bit 15 1 Bit 14 0 Bit 13 1 Bit 12 0 Bit 11 Freq11 Bit 10 Freq10 Bit 9 Freq9 Bit 8 Freq8 Bit 7 Freq7 Bit 6 Freq6 Bit 5 Freq5 Bit 4 Freq4 Bit 3 Freq3 Bit 2 Freq2 Bit 1 Freq1 Bit 0 Freq0
The Frequency Setting Register sets the exact frequency within the selected band for transmit or receive. Each band has a range of frequencies available for channelization or frequency hopping. The selectable frequencies for each band are: Frequency Band 400 MHz 800 MHz 900 MHz Min (MHz) 430.24 860.48 900.72 Max (MHz) 439.75 879.51 929.27 Tuning Resolution 2.5 kHz 5.0 kHz 7.5 kHz
Bit [15..12] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Frequency Setting Register. Bit [11..0] - Frequency Setting: These bits set the center frequency to be used during transmit or receive. The value of bits[11..0] must be in the decimal range of 96 to 3903. Any value outside of this range will cause the previous value to be kept and no frequency change will occur. To calculate the center frequency fc, use Table 9 below and the following equation: fc = 10 * B1 * (B0 + fVAL/4000) MHz where fVAL = decimal value of Freq[11..0] = 96B0 43 43 30
19
Receiver Control Register [POR=9080h]
Bit 15 1 Bit 14 0 Bit 13 0 Bit 12 1 Bit 11 0 Bit 10 INT/VDI Bit 9 VDIR1 Bit 8 VDIR0 Bit 7 BB2 Bit 6 BB1 Bit 5 BB0 Bit 4 GAIN1 Bit 3 GAIN0 Bit 2 RSSI2 Bit 1 RSSI1 Bit 0 RSSI0
The Receiver Control Register configures the following: * Receiver LNA gain * Digital RSSI threshold * Receive baseband bandwidth * Valid Data Detector response time * Function of pin 16 Bit [15..11] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Receiver Control Register. Bit [10] - Pin 16 Func: Selects the function of Pin 16. See Table 10 below. Table 10. Pin 16 Function INT/VDI Interrupt Input 0 Valid Data Output 1 Bit [9..8] - Valid Data Detector Response Time: When Pin 16 is selected as Valid Data Detector output these bits set the response time in which the TRC102 will detect the incoming synchronous bit pattern and issue an interrupt to the host processor. See Table 11 below for response settings. Table 11. VDI Response Time VDIR1 Fast 0 Mid 0 Slow 1 Continuous 1 VDIR0 0 1 0 1
Figure 7. VDI Signal Response Configuration
20
Receiver Control Register - (continued)
Bit [7..5] - Receiver Baseband Bandwidth: These bits set the baseband bandwidth of the demodulated data. The bandwidth can accommodate different FSK deviations and data rates. See Table 12 for bandwidth configuration. Table 12. Baseband BW (kHz) Reserved 400 340 270 200 134 67 Reserved BB2 0 0 0 0 1 1 1 1 BB1 0 0 1 1 0 0 1 1 BB0 0 1 0 1 0 1 0 1
Bit [4..3] - Receiver LNA Gain: These bits set the receiver LNA gain, which can be changed to accommodate environments with high interferers. The LNA gain also affects the true RSSI value. Refer to Bit [2..0] for RSSI. See Table 13 below for gain configuration. Table 13. LNA GAIN (dB) 0 -6 -14 -20 GAIN1 0 0 1 1 GAIN0 0 1 0 1
Bit [2..0] - Digital RSSI Threshold: The digital receive signal strength indicator threshold may be set to indicate that the incoming signal strength is above a preset limit. The result is stored in bit 7 of the status register. There are eight (8) predefined thresholds that can be set. See Table 14 below for settings. Table 14. RSSI2 RSSI1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
RSSI Thresh -103 -97 -91 -85 -79 -73 Not Used Not Used
RSSI0 0 1 0 1 0 1 0 1
The RSSI threshold is affected by the LNA gain set value. Calculate the true RSSI set threshold when the LNA gain is set to a value other than 0 dB as: RSSI = RSSIthres + |GainLNA|
21
Baseband Filter Register [POR=C22Ch]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 1 Bit 8 0 Bit 7 CRLK Bit 6 CRLC Bit 5 1 Bit 4 FILT Bit 3 1 Bit 2 DQLVL2 Bit 1 DQLVL1 Bit 0 DQLVL0
The Baseband Filter Register configures: * Clock Recovery lock control * Baseband Filter type, Digital or Analog RC * Data Quality Detect Threshold parameter Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Baseband Filter Register. Bit [7] - Automatic Clock Recovery Lock: When set, this bit configures the CR (clock recovery) lock control to automatic. In this setting the clock recovery will startup in "Fast" mode and automatically switch to "Slow" mode after locking. See Bit [6] description for details of "Fast" and "Slow" modes. Bit [6] - Manual Clock Recovery Lock Control: When set, this bit configures the CR lock to "Fast" mode. "Fast" mode requires a preamble of at least 6 to 8 bits to determine the clock rate, then locks. When cleared, this bit configures the CR lock to "Slow" mode. "Slow" mode takes a little longer in that it requires a preamble of at least 12 to 16 bits to determine the clock rate, then locks. Use of the "Slow" mode requires more accurate bit timing. See Data Rate Setup Register for the relationship of data rate and CR. Bit [5] - Not Used. Write a "1". Bit [4] - Filter Type: When set, this bit configures the baseband filter as a Digital filter. The Digital filter is a digital version of a simple RC lowpass filter followed by a comparator with hysteresis. The time constant for the Digital filter is automatically calculated internally based on the bit rate as set in the Data Rate Setup Register. When cleared, this bit configures the baseband filter as an Analog RC lowpass filter. The baseband signal is fed to pin 7 thru an internal 10K Ohm resistor. The lowpass cutoff frequency is set by the external capacitor connected from pin 7 to GND. To calculate the baseband capacitor value for a given data rate, use: CFILT = 1 / (30,000*Data Rate) Bit [3] - Not Used. Write a "1". Bit [2..0] - Data Quality Detect Threshold: The threshold parameter should be set less than four (<4) in order for the Data Quality Detector to report good signal quality in the case that the bit rate is close to the deviation. As the data rate << deviation, a higher threshold parameter is permitted and may report good signal quality.
22
FIFO Read Register [POR=B000h]
Bit 15 1 Bit 14 0 Bit 13 1 Bit 12 1 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Bit 7 RX7 Bit 6 RX6 Bit 5 RX5 Bit 4 RX4 Bit 3 RX3 Bit 2 RX2 Bit 1 RX1 Bit 0 RX0
The FIFO Read Register stores the received data and can be read out by the host processor. The FIFO must be enabled by setting Bit[6] of the Configuration Register. Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Data FIFO Configuration Register. Bit [7..0] - FIFO Data Bits: These bits are the recovered data bits stored in the FIFO. These bits may be read out over the SPI bus.
*Alternate Read Method
The Rx FIFO is directly accessible by using the nFSEL select pin (6) and monitoring the FINT interrupt pin (7) for pending data. Each data bit may be clocked in on the rising edge of SCK.
nCS SCK SDO nFSEL nFINT
D7 D6 D5 D4 D3 D2 D1 D0
Figure. 8 Recommended FIFO Read Method Timing
*NOTE: The internal FIFO cannot be accessed faster than fXTAL/4 when reading the FIFO or data errors will occur. For a 10MHz ref xtal the max SCK <2.5MHz.
23
FIFO and RESET Mode Configuration Register [POR=CA80h]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 1 Bit 10 0 Bit 9 1 Bit 8 0 Bit 7
FINT3
Bit 6
FINT2
Bit 5
FINT1
Bit 4
FINT0
Bit 3
SBL
Bit 2
FIFST
Bit 1
FILLEN
Bit 0
RSTEN
The Data FIFO Configuration Register configures: * FIFO fill interrupt condition * FIFO fill start condition * FIFO fill on synchronous pattern * Synchronous Character Length * RESET Mode Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Data FIFO Configuration Register. Bit [7..4] - FIFO Fill Bit Count: This sets the number of bits that are received before generating an external interrupt to the host processor that the receive FIFO data is ready to be read out. It is possible to set the maximum fill level to 15, but the designer must account for the processing time it will take to read out the data before a register overrun occurs, at which data will be lost. It is recommended to set the fill value to half of the desired number of bits to be read to ensure enough time for additional processing. See Status Register for description of FIFO status bits that may be read and FIFO Read Register for polling and interrupt-driven FIFO reads from the SPI bus. Bit [3] - Synchronous Character Length: This bit sets the length of the synch character to either byte or word long. When set to word long the character is composed of 2 bytes SB1 and SB0. The value of SB1 is fixed and is not configurable. The value of SB0 is user programmable through the Synch Byte Configuration Register. When set to byte long only SB0 is used and is user programmable. Note: Default POR value of SB0 is D4h. Table 15. Synch Character SBL SB1 SB0 2DXX (Word Long) 0 2D D4 (programmable) XX (Byte Long) 1 N/A D4 (programmable) Bit [2] - FIFO Fill Start Condition: This bit sets the condition at which the FIFO begins filling with data. When set, the FIFO will continuously fill regardless of noise or good data. When clear, the FIFO will fill when it recognizes the synchronous pattern as defined internally. Bit [1] - Synchronous Pattern FIFO Fill: When set, the FIFO will begin filling with data when it detects the synchronous pattern as defined in Bit [2]. The FIFO fill stops when this bit is cleared. To restart the synchronous pattern recognition, simply clear the bit and set again. Note: Clearing this bit will issue a FIFO reset. See Figure 9 for FIFO write and reset configuration.
24
Figure 9. FIFO Write and Reset Configuration
Bit [0] - Disable RESET Mode: When cleared, if the TRC102 encounters a 0.2V spike in the power supply, the glitch could cause a system reset. When set, this mode is disabled.
25
Synch Byte Configuration Register [POR=CED4h]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 1 Bit 10 1 Bit 9 1 Bit 8 0 Bit 7
SYNC7
Bit 6
SYNC6
Bit 5
SYNC5
Bit 4
SYNC4
Bit 3
SYNC3
Bit 2
SYNC2
Bit 1
SYNC1
Bit 0
SYNC0
The Synch Byte Configuration Register assigns the value to SB0 of the synchronous character in the FIFO and RESET Mode Configuration Register. This value is valid for a byte or word long synch character.
26
Data Rate Setup Register [POR=C623h]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 1 Bit 9 1 Bit 8 0 Bit 7 PRE Bit 6 BITR6 Bit 5 BITR5 Bit 4 BITR4 Bit 3 BITR3 Bit 2 BITR2 Bit 1 BITR1 Bit 0 BITR0
The Data Rate Setup Register configures: * Expected data rate for the receiver * Prescaler * Effects of the data rate on clock recovery Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Data Rate Setup Register. Bit [7] - Prescaler Enable: When set this bit enables the prescaler to obtain smaller values of expected data rates. The prescaler value is approximately 1/8. Bit [6..0] - Data Rate Parameter Value: These bits represent the decimal value of the 7-bit parameter used to calculate the expected data rate. To calculate the expected data rate, use the following formula: DRexp(kbps) = 10000 / [29 * (BITR[6..0]+1) * (1+PRE*7)] where BITR[6..0] is the decimal value 0 to 127 and the prescaler (PRE) is `1' (on) or `0' (off). To calculate the BITR[6..0] decimal value for a given bit rate, use the following formula: BITR[6..0] = 10000 / [29 * (1+PRE*7) * DRexp where DRexp is the expected data rate and PRE is defined above. Without the prescaler, the definable data rates range from 2.694kpbs to 344.828kbps. With the prescaler enabled, the definable data rates range from 337 bps to 43.103kpbs. The Slow clock recovery mode requires more accurate bit timing when setting the data rate. To calculate the accuracy of the data rate for both Fast and Slow mode, use the following: Slow mode Acc = BR/BR < 1/(29 * N) Fast mode = BR/BR < 3/(29 * N)
where N is the longest number of expected ones or zeros in the data stream, BR is the difference in the actual data rate vs. the set data rate in the transmitter, and BR is the expected data rate as set above using BITR[6..0].
27
Power Management Register [POR=8208h]
Bit 15 1 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 1 Bit 8 0 Bit 7 RXEN Bit 6 BBEN Bit 5 TXEN Bit 4 SYNEN Bit 3 OSCEN Bit 2 LBDEN Bit 1 WKUPEN Bit 0 CLKEN
The Power Management Register enables/disables the following: * Receiver chain * Transmit Chain * Baseband Circuit * PLL * Power Amplifier * Synthesizer * Crystal Oscillator * Low battery Detect Circuit * Wake-up Timer * Clock Output Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Power Management Register. Bit [7] - Receiver Chain Enable: This bit enables the entire receiver chain when set. The receiver chain comprises the baseband circuit, synthesizer, and crystal oscillator. Bit [6] - Baseband Circuit Enable: This bit enables the baseband circuit when set. The baseband circuit, synthesizer, and oscillator work together to demodulate and recover the data transmitted so the synthesizer (Bit 4) and oscillator (Bit 3) must be enabled at the same time as the baseband circuits in order to receive data. This bit can be disabled to conserve current consumption. Bit [5] - Transmit Chain Enable: This bit enables the entire transmit chain when set. The transmit chain consists of the power amplifier, synthesizer, oscillator, and transmit register. When the transmit chain and transmit register is enabled, any data in the transmit register is shifted out and transmission is started. Bit [4] - Synthesizer Enable: This bit enables the synthesizer when set. The synthesizer contains the PLL, oscillator, and VCO for controlling the channel frequency. This must be enabled when either the transmitter is enabled or the receiver is enabled. The oscillator also must be enabled to provide the reference frequency for the PLL. On power-up the synthesizer performs a calibration automatically. If there are significant changes in voltage or temperature, recalibration can be performed by simply disabling the synthesizer and re-enabling it. Bit [3] - Crystal Oscillator: This bit enables the oscillator circuit when set. The oscillator provides the reference signal for the synthesizer when setting the transmit or receive frequency of use. Bit [2] - Low Battery Detector: This bit enables the battery voltage detect circuit when set. The battery detector can be programmed to 32 different threshold levels. See Battery Detect Threshold and Clock Output Register section for programming. Bit [1] - Wake-up Timer Enable: This bit enables the wake-up timer when set. See Wake-up Timer Period Register section for programming the wake-up timer interval value. Bit [0] - Clock Output Disable: This bit disables the oscillator clock output when set. On chip reset or power up, clock output is enabled so that a processor may begin execution of any special setup sequences as required by the designer. See Battery Detect Threshold and Clock Output Register section for programming details.
28
Wake-up Timer Period Register [POR=E196h]
Bit 15 1 Bit 14 1 Bit 13 1 Bit 12 R4 Bit 11 R3 Bit 10 R2 Bit 9 R1 Bit 8 R0 Bit 7 M7 Bit 6 M6 Bit 5 M5 Bit 4 M4 Bit 3 M3 Bit 2 M2 Bit 1 M1 Bit 0 M0
The Wake-up Timer Period register sets the wake-up interval for the TRC102. After setting the wake-up interval, the WKUPEN (bit 1 of Power Management Register) should be cleared and set at the end of every wake-up cycle. To calculate the wake-up interval desired, use the following: TWAKE(ms) = M[7..0] * 2 R[4..0] where M[7..0] = decimal value 0 to 255 and R[4..0] = decimal value 0 to 31. Bit [15..13] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Wake-up Timer Period register. Bit [12..8] - Exponential: These bits define the exponential value as used in the above equation. The value used must be the decimal equivalent between 0 and 31. Bit [7..0] - Multiplier: These bits define the multiplier value as used in the above equation. The value used must be the decimal equivalent between 0 and 255.
29
Duty Cycle Set Register [POR=C80Eh]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 1 Bit 10 0 Bit 9 0 Bit 8 0 Bit 7 DC6 Bit 6 DC5 Bit 5 DC4 Bit 4 DC3 Bit 3 DC2 Bit 2 DC1 Bit 1 DC0 Bit 0 DCEN
The duty cycle register may be used in conjunction with the wake-up timer to reduce the average current consumption of the receiver. The duty cycle register may be set up so that when the wake-up timer brings the chip out of sleep mode the receiver is turned on for a short time to sample if a signal is present and then goes back into sleep and the process starts over. The duty cycle uses the Multiplier value of the wake-up timer in part for its calculation. To calculate the duty cycle use: Duty Cycle(%) = ((D[6..0] * 2 )+ 1)/M * 100 where M is M[7..0] of the Wake-up Timer Period Register. Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Duty Cycle Set Register. Bit [7..1] - Duty Cycle Multiplier: These bits are the decimal value used to calculate the Duty Cycle or "On time" of the Receiver after the wake-up timer has brought the TRC102 out of sleep mode. Bit [0] - Duty Cycle Mode Enable: This bit enables the duty cycle mode when set. NOTE: The receiver must be disabled (RXEN = `0' in Power Management Register) and the wake-up timer must be enabled (WKUPEN = `1' in Power Management Register) for operation in this mode.
30
Battery Detect Threshold and Clock Output Register [POR=C000h]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Bit 7 CLK2 Bit 6 CLK1 Bit 5 CLK0 Bit 4 0 Bit 3 LBD3 Bit 2 LBD2 Bit 1 LBD1 Bit 0 LBD0
The Battery Detect Threshold and Clock Output Register configures the following: * Low Battery Detect Threshold * Output Clock frequency The Low Battery Threshold is programmable from 2.2V to 3.8V using the following equation: VT = (LBD[4..0] / 10) + 2.2 (V) where LBD[3..0] is the decimal value 0 to 15. Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the Battery Detect Threshold and Clock Output Register. Bit [7..5] - Clock Output Frequency: These bit set the output frequency of the on-board clock that may be used to run an external host processor. See Table 16 below. TABLE 16. Output Clock Frequency (MHz) 1 1.25 1.66 2 2.5 3.33 5 10 CLK2 0 0 0 0 1 1 1 1 CLK1 0 0 1 1 0 0 1 1 CLK0 0 1 0 1 0 1 0 1
Bit [4..0] - Low Battery Detect Value: These bits set the decimal value as used in the equation above to calculate the value of the battery detect threshold voltage. When the battery level falls 50mV below this value, the LBD bit (5) in the status register is set indicating that the battery level is below the programmed threshold. This is useful in monitoring discharge sensitive batteries such as Lithium cells. The Low Battery Detect can be enabled by setting the LBDEN bit (2) of the Power Management Register and disabled by clearing the bit. The Clock Output can be enabled by setting the CLKEN bit (0) of the Power Management Register and disabled by clearing the bit.
31
PLL Configuration Register [POR=CC67h]
Bit 15 1 Bit 14 1 Bit 13 0 Bit 12 0 Bit 11 1 Bit 10 1 Bit 9 0 Bit 8 0 Bit 7 0 Bit 6 BUF1 Bit 5 BUF0 Bit 4 XSU Bit 3 PDD Bit 2 DITH Bit 1 1 Bit 0 PLLBW
The PLL Configuration Register configures the following: * Output Clock buffer slew rate * Crystal start-up time * Phase Detector Delay (PDD) * PLL Dithering * PLL Bandwidth Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be written to the PLL Configuration Register. Bit [7] - Not Used: Write a `0'. Bit [6..5] - Clock Buffer Slew: These bits set the rise and fall times for the clock buffer dependant on the output frequency. See table 17 below. Table 17. Freq BUF1 BUF0 >5 MHz 0 0 3 MHz 0 1 <2.5 MHz 1 X Bit [4] - Crystal Start-up Time: This bit sets the start-up time and current consumption of the crystal. See table 18 below. Table 18. Time Current XSU 1ms 620uA 0 2 ms 460uA 1 Bit [3] - Phase Detector Delay: When set, this bit enables the delay function. Bit [2] - PLL Dithering: When set, this bit disables dithering. Dithering reduces the noise error when calculating the fractional-N synthesizer code. When clear, dithering is enabled and settle time is increased slightly. Bit [1] - Not Used: Write a `1'. Bit [0] - PLL Bandwidth: When set, this bit increases the PLL bandwidth slightly to accommodate higher data rates above 90kbps. When clear, the PLL bandwidth is reduced which allows for faster settling and reduced phase noise resulting in better RX performance. See Table 19 below. Data Rate <90 kbps >90 kbps Table 19. Phase Noise -107 dBc/Hz -102 dBc/Hz
PLLBW 0 1
32
5. Maximum Ratings Absolute Maximum Ratings
Symbol
VDD Vin Voc Iin ESD Tstg Tlead
Parameter
Positive supply voltage Voltage on any pin (except RF_P and RF_N) Voltage on open collector outputs (RF1, RF2) Input current into any pin except VDD and VSS Electrostatic discharge with human body model Storage temperature Lead temperature (soldering, max 10 s)
Notes
Min
-0.5 -0.5
Max
6 Vdd+0.5 Vdd+1.5 25 1000 125 260
Units
V V V mA V C C
1
-0.5 -25 -55
Note 1: At maximum, VDD+1.5 V cannot be higher than 7 V.
Recommended Operation Ratings
Symbol
VDD VDCRF VACRF Top
Parameter
Positive supply voltage DC voltage on open collector outputs (RF1, RF2) AC peak voltage on open collector outputs (RF1, RF2) Ambient operating temperature
Notes
1,2 1
Min
2.2 Vdd-1.5 Vdd-1.5 -40
Max
3.8 Vdd+1.5 Vdd+1.5 85
Units
V V V C
Note 1: At minimum, VDD - 1.5 V cannot be lower than 1.2 V. Note 2: At maximum, VDD+1.5 V cannot be higher than 5.5 V.
6. DC Electrical Characteristics
(Min/max values are valid over the recommended operating range Vdd = 2.2-3.8V. Typical conditions: Top = 27C; Vdd = 3.0 V) Limit Sym Notes Unit Test Conditions Current Values min typ max Parameter Sleep current IS 0.3 A All blocks disabled Oscillator and baseband Idle current IIDLE 0.6 mA enabled Low battery detector current consumption IVD 0.5 A Wake-up timer current consumption IWUT 1.5 A Programmable in 0.1 V Low battery detect threshold Vlb 2.2 3.7 V steps Low battery detection accuracy 50 mV Analog RSSI Output Level RSSI 300 1000 mV -50dBm>RFin>-115dBm 15 433MHz Band Supply current (TX mode, Pout = 0dBm, Idd_TX0 mA 16 868MHz Band 50 Ohm Load) 17 916MHz Band 21 433MHz Band Supply current (TX mode, Pout = Pmax) Idd_TX mA 22 868MHz Band 23 916MHz Band 11 433MHz Band Supply current (RX mode) Idd_RX mA 12 868MHz Band 13 916MHz Band Limit Values min Vil Vih Iil Iih Vol Voh Vdd-0.4 2 10 0.7*Vdd -1 -1 1 1 0.4 typ max 0.3*Vdd V V A A V V pF ns Load = 15 pF Vil = 0 V Vih = Vdd, Vdd = 5.4 V Iol = 2 mA Ioh = -2 mA
Digital I/O
Parameter
Digital input low level Digital input high level Digital input current low Digital input current high Digital output low level Digital output high level Digital input capacitance Digital output rise/fall time
Sym
Notes
Unit
Test Conditions
33
7. AC Electrical Characteristics
(Min/max values are valid over the recommended operating range Vdd = 2.2-3.8V. Typical conditions: Top = 27C; Vdd= 3.0V) Limit Notes Sym Unit Test Conditions Receiver Values min typ max Parameter RF input impedance (real,differential) Maximum input power Receiver bandwidth 0 67 -112 -110 -109 400 250 Ohms dBm kHz 433MHz Band 868MHz Band 916MHz Band LNA gain (0 dB, -14 dB) LNA Max gain
Receiver Sensitivity
1
dBm
IIP3 In band interferers (-95dBm carrier,<1MHz offset,CW)
3
-49 -48 -47 -39 -46 -27 0.6 0.8*dev 1 100 350 +/-5 46 6 115.2 256
dBm
433MHz Band 868MHz Band 916MHz Band 433MHz Band
IIP3 Out of band interferers (-95dBm carrier,>10 MHz offset,CW)
dBm
868MHz Band 916MHz Band Digital filters Analog filter dev = FSK deviation
FSK bit rate AFA lock range RF input capacitance Analog RSSI Filter Cap Analog RSSI deviation RSSI accuracy RSSI dynamic range RSSI programmable threshold steps
kbps kHz pF pF mV dB dB dBm
LNA Gain = max, RFin<-60dBm
Digital RSSI response time
<100
us
RSSI signal goes high after input signal exceeds programmed limit. CAPARRSI = 1pF 433 MHz Band 868 MHz Band 916 MHz Band
Spurious emission (@ Pmax)
<95
dBm
34
AC Electrical Characteristics - continued
(Min/max values are valid over the recommended operating range Vdd = 2.2-3.8V. Typical conditions: Top = 27C; Vdd = 3.0 V)
Transmitter
Parameter
FSK bit rate FSK frequency deviation
Sym
Notes
Limit Values
Unit
Test Conditions
min
15
typ
max
256 240 kbps kHz Programmable in 15 kHz steps 433 MHz Band 868 MHz Band 916 MHz Band 433 MHz Band 868 MHz Band 916 MHz Band 6 mA Programmable
Output power (into 50 Ohms)
Pmax
+7 +5 +4.5
dBm
Output power (into differential load)
5
+7 +7 +7
dBm
Open collector output DC current
0.5
Reference Spur (@ Pmax)
-47 -39 -39 -41 -40 -38 -38 -41 -48 2 2.6 2.7 15 10 -80 -103 3.2
dBm
433MHz Band 868MHz Band 916MHz Band 433MHz Band 868MHz Band 916MHz Band 433MHz Band 868MHz Band 916MHz Band 433MHz Band 868MHz Band 916MHz Band 433MHz Band 868MHz Band 916MHz Band 100 kHz from carrier 1 MHz from carrier
2nd Harmonics (@ Pmax)
dBm
3rd Harmonics (@ Pmax)
dBm
Antenna tuning capacitance 2.1 3.3
pF
Output Capacitance Quality factor
Phase noise
dBc/Hz
35
AC Electrical Characteristics - continued
(Min/max values are valid over the recommended operating range Vdd = 2.2-3.8V. Typical conditions: Top = 27C; Vdd = 3.0 V)
Timing
Parameter
Transmit to Receive switch time Receive to Transmit switch time Sleep to Receive Sleep to Transmit POR timeout Wake-up timer clock period
Sym
Notes min
Limit Values typ
250 150 250 150 1.25 1.25
Unit max
us us us us ms ms 100 ms ms
Test Conditions
Synthesizer off, osc on, 10 MHz step Both ON, 10 MHz step Synthesizer off, osc on, 10 MHz step Both ON, 10 MHz step SPI Command to Receive Bit SPI Command to Transmit Bit Vdd at 90% of final value Calibrated every 30 seconds
1
PLL Characteristics
Parameter
PLL reference freq PLL lock time PLL startup time Crystal load capacitance Xtal oscillator startup time Frequency Range (w/ 10MHz ref xtal)
Sym
fREF
Notes min
2 8
Limit Values typ
10 10
Unit max
12 250 MHz us us pF ms 439.75 879.51 929.27
Test Conditions
within 1kHz settle, 10MHz step Crystal running Programmable in 0.5 pF steps, tolerance +/- 10% Crystal ESR < 100 Ohms 433MHz Band (2.5kHz steps) 868MHz Band (5.0kHz steps) 916MHz Band (7.5kHz steps)
CL
8.5 1 430.24 860.48 900.72
16
MHz
NOTES: 1- BW=67 kHz, f=30kHz, BER=1 to 3 x10-3, Data Rate=2.4 kbps, digital filter, AFA disabled. 2- Other crystal frequencies may be used, but every function on chip, including wake-up timer, output clock, data rate, clock recovery, etc..., is dependent on this reference frequency and everything will scale accordingly. 3- FCC Class 2 Blocking. 4- Load equivalent to a tuned Loop or Dipole Antenna at the required operating frequency.
36
8. Receiver Measurement Results
The sensitivity measurements were derived from the Typical Application Circuit of Figure 1, pg 4, and the layout as suggested on pg 6. All data rates are based on a 10-3 BER.
Sensitivity vs Data Rate
-113 -111 -109 -107 -105 Sensitivity (dBm) -103 -101 -99 -97 -95 -93 -91 -89 1200 2400 4800 9600 19200 38400 57600 115000 Data Rate (bps)
433MHz
915MHz
868MHz
Sensitivity vs Receive Bandwidth
-109
433MHz
-107
-105 Sensitivity (dBm)
915MHz 868MHz
-103
-101
-99
-97 67 200 Bandwidth (kHz) 405
37
Receive Current vs Voltage (2.4kbps)
14.0
915MHz
13.0
Current (mA)
868MHz 433MHz
12.0
11.0
10.0 2.2 3 Voltage (V) 3.8
38
9. Transmitter Measurement Results
The transmitter measurements were derived from the Typical Application Circuit of Figure 1, pg 4, and the layout as suggested on pg 6.
Voltage vs Output Power
8.0
433MHz
7.0
6.0 Output Power (dBm)
868MHz 915MHz
5.0
4.0
3.0
2.0
1.0 2.2 3 Voltage (V) 3.8
Current vs Operating Voltage (Max Output Power)
25.0
915MHz
24.0
868MHz
Current (mA)
23.0
433MHz
22.0
21.0
20.0 2.2 3 Voltage (V) 3.8
39
10.0 Package Dimensions - 6.4x5mm 16-pin TSSOP Package
(all values in mm)
Detail
A
C
B
2
0.20
F
G Gauge Plane
R1 R
D
E
1
0.25
3
L L1
Detail
Symbol A B C D E F G L L1 R R1 1 2 3
4441 Sigma Road Dallas, Texas 75244 (800) 704-6079 toll-free in U.S. and Canada Email: info@rfm.com www.rfm.com www.wirelessis.com
Dimensions in mm Min Nom Max 4.30 4.40 4.50 4.90 5.00 5.10 6.40 BSC. 0.19 0.30 0.65 BSC. 0.80 0.90 1.05 1.20 0.50 0.60 0.75 1.00 REF. 0.09 0.09 0 8 12 REF. 12 REF.
Dimensions in Inches Min Nom Max 0.169 0.173 0.177 0.193 0.197 0.201 0.252 BSC. 0.007 0.012 0.026 BSC. 0.031 0.035 0.041 0.47 0.020 0.024 0.030 0.39 REF 0.004 0.004 0 8 12 REF. 12 REF.
(c) 2006 RF Monolithics, Inc. TRC102 2006-10-27
Rev04
40

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